Altera DSP Development Kit, Cyclone II Edition Getting Started - Manual (Page 25)

Altera Corporation Getting Started User Guide 2–15
August 2006 DSP Development Kit, Cyclone II Edition
Getting Started
Testing the
Board Using the
Factory Design Put the Cyclone II DSP development board in SAFE configuration mode
by putting a jumper on J29, pins 1 and 2. Then apply power and the
Cyclone II device will be configured with the factory design stored in the
EPCS64 flash memory, serial configuration device (U17). When
configuration is complete, LEDs D9 through D5 (
USER_LED0 through
USER_LED4, respectively), flash yellow, functioning as a binary counter
that counts down to zero. This indicates that the Cyclone II DSP
development board is functional and the EP2C70 device was successfully
configured with the factory design.
If the Cyclone II DSP development board does not start as described
above, follow these steps:
■ Turn off the power to the board by placing SW1 (POWER switch) in
the OFF position.
■ Place the board in SAFE configuration mode by placing a jumper on
pins 1 and 2 on jumper J29.
■ Power-up the board by placing SW1 (POWER switch) in the ON
position.
c
If you overwrite the factory design stored on U17, refer to the
Restoring the Factory Design appendix in the Cyclone II DSP
Development Board Reference Manual.
Understanding the Factory Design
In the factory design, two sine waves are generated by two instances of
the Altera numerically controlled oscillator (NCO) MegaCore. One of
these oscillators is running at 10 times the frequency of the other, but both
of them have the same amplitude, covering 13 bits of dynamic range. The
two sine waves output from these blocks are added together and the
output is converted from a two’s complement representation into
unsigned integer format. This combined sine wave signal of 14-bits
dynamic range is sent to a 14-bit D/A converter. The analog output of a
D/A converter is connected, via the included SMA cable, with the analog
input of a 12-bit A/D converter. The A/D converter’s digital output is
looped back to the Cyclone II device. The design converts this loopback
input from two’s complement format to unsigned integer format. The
converted loopback data is captured by an instance of the SignalTap
® II
logic analyzer in the design for display and analysis. Figure 2–7 shows a
high-level view of the factory design and how it interacts with the D/A
and A/D converters on the Cyclone II DSP development board in the
following sections.