Fir ii ip core functional description, Fir ii ip core interfaces and signals, Fir ii ip core functional description -1 – Altera FIR Compiler II MegaCore Function User Manual

Page 34: Fir ii ip core interfaces and signals -1

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FIR II IP Core Functional Description

4

2014.12.15

UG-01072

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The FIR II IP core generates the Avalon-ST register transfer level (RTL) wrapper.

Figure 4-1: High Level Block Diagram of FIR II IP core with Avalon-ST Interface

FIR

Filter

xln_v

bankln_0[]

xln_(n-1)[]

xOut_v

xOut_c

xOut_0[]

xOut_(m-1)[]

ast_sink_valid

ast_sink_data[]

ast_sink_sop

ast_sink_eop

ast_sink_error

ast_source_valid

ast_source_data[]

ast_source_sop

ast_source_eop

ast_source_error

ast_source_channel

Controller

ast_sink_ready

ast_source_ready

FIR Compiler II MegaCore Function

Sink

Source

control signals

control signals

control signals

xln_0[]

bankln_(n-1)[]

FIR II IP Core Interfaces and Signals

The IP core uses an interface controller for the Avalon-ST wrapper that handles the flow control

mechanism. The IP core communicates control signals between the sink interface, FIR filter, and source

interface via the controller. When designing a datapath that includes the FIR II IP core, you might not

need backpressure if you know the downstream components can always receive data. You might achieve a

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