About the fir ii ip core, Altera dsp ip core features, About the fir ii ip core -1 – Altera FIR Compiler II MegaCore Function User Manual
Page 4: Altera dsp ip core features -1
About the FIR II IP Core
1
2014.12.15
UG-01072
The Altera
®
FIR II IP core provides a fully-integrated finite impulse response (FIR) filter function
optimized for use with Altera FPGA devices. The II IP core has an interactive parameter editor that allows
you to easily create custom FIR filters. The parameter editor outputs IP functional simulation model files
for use with Verilog HDL and VHDL simulators.
You can use the parameter editor to implement a variety of filter types, including single rate, decimation,
interpolation, and fractional rate filters.
Many digital systems use signal filtering to remove unwanted noise, to provide spectral shaping, or to
perform signal detection or analysis. FIR filters and infinite impulse response (IIR) filters provide these
functions. Typical filter applications include signal preconditioning, band selection, and low-pass
filtering.
Figure 1-1: Basic FIR Filter with Weighted Tapped Delay Line
xin
yout
Z
-1
Z
-1
Z
-1
Z
-1
Tapped
Delay Line
Coefficient
Multipliers
Adder Tree
C
0
1
C
0
2
C
1
1
C
1
2
C
2
1
C
2
2
C
3
1
C
3
2
Coefficient
Banks
To design a filter, identify coefficients that match the frequency response you specify for the system. These
coefficients determine the response of the filter. You can change which signal frequencies pass through
the filter by changing the coefficient values in the parameter editor.
Altera DSP IP Core Features
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