Altera FIR Compiler II MegaCore Function - Manual (Page 35)

higher clock rate by driving the
ast_source_ready
signal of the FIR II IP core high, and not connecting
the
ast_sink_ready
signal.
The sink and source interfaces implement the Avalon-ST protocol, which is a unidirectional flow of data.
The number of bits per symbol represents the data width and the number of symbols per beat is the
number of channel wires. The IP core symbol type supports signed and unsigned binary format. The
ready latency on the FIR II IP core is 0.
The clock and reset interfaces drive or receive the clock and reset signals to synchronize the Avalon-ST
interfaces and provide reset connectivity.
Related Information
Avalon Interface Specifications
For more information about the Avalon-ST interface properties, protocol and the data transfer timing
Avalon-ST Interfaces in DSP IP Cores
Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source
interface to a sink interface.
The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source. The Avalon-ST
interface supports packet transfers with packets interleaved across multiple channels.
Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of
data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready,
and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packet
transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchro‐
nizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations
without having to implement complex control logic.
Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can signal to
a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO
buffers are full or when it has congestion on its output.
Related Information
• Avalon Interface Specifications
FIR II IP Core Avalon-ST Interfaces
Avalon-ST Sink Interface
The sink interface can handle single or multiple channels on a single wire and multiple channels on
multiple wires.
4-2 Avalon-ST Interfaces in DSP IP Cores
UG-01072
2014.12.15
Altera Corporation FIR II IP Core Functional Description
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