Infer megafunctions from hdl code, Instantiate megafunctions in hdl code – Altera Shift Register IP Core User Manual

Page 6

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Description

Function

Some files are automatially selected by the MegaWizard Plug-In Manager.
The choices are:

• Variation file, (<function name>

.v

/

.vhd

/

.tdf

)

• Block Symbol file (

.bsf

)

• Instantiation template file (<function name>

_inst.v

)

• VHDL component declaration file (<function name>

.cmp

)

• Verilog Black Box declaration file (<function name>

_bb.v

)

Turn on the files you wish to
generate.

Related Information

Ports and Parameters

on page 12

Infer Megafunctions from HDL Code

Synthesis tools, including the Quartus II integrated synthesis, recognize specific types of HDL code,
automatically inferring the appropriate megafunction when a megafunction will provide optimal results.
The Quartus II software uses the Altera

®

megafunction code when compiling your design, even if it was not

specifically instantiated. The Quartus II software infers megafunctions which are optimized for Altera devices,
so the area and/or performance may be better than generic HDL code. Use megafunctions to access Altera
architecture-specific features, such as memory, DSP blocks, and shift registers, providing improved
performance compared with basic logic elements.

Related Information

Recommended HDL Coding Styles

Instantiate Megafunctions in HDL Code

You can instantiate a megafunction directly in your Verilog HDL, or VHDL, code by calling the megafunction
and setting its parameters as you would in any other module, component, or subdesign. When instantiating
a megafunction in VHDL, be sure to include the correct libraries.

When you use the MegaWizard Plug-In Manager to set up and parameterize a megafunction, it creates either
a VHDL or Verilog HDL wrapper file that instantiates the megafunction (a black-box methodology). For
some megafunctions, you can generate a fully synthesizable netlist for improved results with EDA synthesis
tools, such as Synplify and Precision RTL Synthesis (a clear-box methodology). Both clear-box and black-box
methodologies are described in the third-party synthesis support chapters in the Quartus II Handbook.

Related Information

Recommended HDL Coding Styles

Quartus II Integrated Synthesis

Synopsys Synplify Support

Mentor Graphics Precision Synthesis Support

LPM_SHIFTREG Megafunction

Altera Corporation

Feedback

UG-033105

Infer Megafunctions from HDL Code

6

2013.03.05

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