Altera Shift Register IP Core - Manual (Page 7)

LPM_SHIFTREG AHDL Function Prototype
The following AHDL function prototype is located in the AHDL Include File ( .inc ) lpm_shiftreg.inc in the
<Quartus II installation directory>\libraries\megafunctions directory.
Port name and order also apply when used in Verilog HDL. Note:
FUNCTION lpm_shiftreg (data[LPM_WIDTH-1..0], clock, enable,
shiftin, load,
sclr, sset,
aclr, aset)
WITH (LPM_WIDTH, LPM_DIRECTION, LPM_AVALUE, LPM_SVALUE)
RETURNS(q[LPM_WIDTH-1..0], shiftout);
LPM_SHIFTREG VHDL Component Declaration
The following VHDL component declaration is located in the VHDL Design File ( .vhd ) LPM_PACK.vhd in
the <Quartus II installation directory>\libraries\vhd\lpm directory.
component LPM_SHIFTREG
generic (LPM_WIDTH : natural; -- MUST be greater than 0
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_DIRECTION: string := "UNUSED";
LPM_TYPE: string := L_SHIFTREG;
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0)
:= (OTHERS => '0');
CLOCK : in std_logic;
ENABLE : in std_logic := '1';
SHIFTIN : in std_logic := '1';
LOAD : in std_logic := '0';
SCLR : in std_logic := '0';
SSET : in std_logic := '0';
ACLR : in std_logic := '0';
ASET : in std_logic := '0';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0);
SHIFTOUT : out std_logic);
end component;
The following VHDL LIBRARY-USE declaration is not required if you use the VHDL Component Declaration.
LIBRARY altera_mf;
USE lpm.lpm_components.all;
Altera Corporation LPM_SHIFTREG Megafunction
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7 LPM_SHIFTREG AHDL Function Prototype
UG-033105
2013.03.05