Altera Shift Register IP Core - Manual (Page 8)

Simulating Megafunctions
Simulation verifies design behavior before device programming. The Quartus II software supports RTL and
gate level design simulation of megafunction IP cores in other EDA simulators. Simulation involves setting
up your simulator working environment, compiling simulation model libraries, and running your simulation.
Altera provides various tools to help you quickly setup and run simulation. You can use the Quartus II
NativeLink feature to automatically generate simulation files and scripts. NativeLink launches your preferred
simulator a from within the Quartus II software.
Use a custom flow for more control over all aspects of simulation file generation. Alternatively, the Simulation
Library Compiler automatically compiles and stores the correct simulation model libraries for functional
and gate-level timing simulation of your design.
Related Information
Simulating Altera Designs
Debugging with the SignalTap II Embedded Logic Analyzer
The SignalTap ® II embedded logic analyzer provides a method of debugging the Altera megafunctions
within your design. With the SignalTap II embedded logic analyzer, capture and analyze data samples for
top-level ports of the megafunctions in your design while your system is running at full speed.
To monitor signals from your megafunctions, first configure the SignalTap II embedded logic analyzer in
the Quartus II software, and include the analyzer as part of your project. The Quartus II software seamlessly
embeds the analyzer with your design in the selected device.
Related Information
Design Debugging Using the SignalTap II Logic Analyzer
Design Example: Configurable 8Bit SIPO or PISO Shift Register
This design example uses the LPM_SHIFTREG megafunction to implement a configurable 8-bit serial in
parallel out (SIPO) or parallel in serial out (PISO) shift register. In this example, you create an 8-bit SIPO
or PISO shift register.
• Generating an 8-bit shift register using the LPM_SHIFTREG megafunction and the MegaWizard Plug-in
Manager.
• Implement design and assign the 5SGMD4E1H29C1 Stratix V GS device to the project.
• Compile and simulate the design.
Design Files
The design files are available in the Quartus II Projects section on the Design Examples page of the Altera
web site: Select the “Examples for lpm_shiftreg Megafunction User Guide” link from the examples page to
download the design files.
Related Information
Design Examples
LPM_SHIFTREG Megafunction Altera Corporation
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Simulating Megafunctions 8
2013.03.05