Altera Data Conversion HSMC - Manual (Page 15)

Chapter 2: Board Components and Interfaces 2–9
Component Interfaces
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
A/D Converter Clocks
Figure 2–5 shows the components involved in selecting the clock signal to be sent to
the AD9254 A/D converter (U1 for channel A, U2 for channel B). J3 (channel A) or J7
(channel B) selects the A/D clock from the FPGA clock A, the FPGA clock B, or the
external SMA clock (J26 and J30). The selected A/D clock passes through a differential
to LVDS clock multiplexer (U9 for channel A, U10 for channel B), which provides the
clock signal to the AD9254.
ADB_D4 68 D4 3 Data Output Bit 4
ADB_D5 66 D5 4 Data Output Bit 5
ADB_D6 62 D6 5 Data Output Bit 6
ADB_D7 60 D7 6 Data Output Bit 7
ADB_D8 56 D8 9 Data Output Bit 8
ADB_D9 54 D9 10 Data Output Bit 9
ADB_D10 50 D10 11 Data Output Bit 10
ADB_D11 48 D11 12 Data Output Bit 11
ADB_D12 44 D12 13 Data Output Bit 12
ADB_D13 42 D13 14 Data Output Bit 13
ADB_OR 84 OR 15 Out-of-Range Indicator
AD_SDIO 91 SDIO/DCS 18 Serial Port Interface (SPI) Data
Input/Output (Serial Port Mode)
AD_SCLK 92 SCLK/DFS 19 Serial Port Interface Clock (Serial Port
Mode)
ADB_SPI_CS 90 CSB 20 Serial Port Interface Chip Select
(Active Low)
ADB_OE 86 OEB 43 Output Enable (Active Low)
ADB_DCO 158 DCO 44 Data Clock Output
— — ADB_CLK_P 38 (1) Clock Input
— — ADB_CLK_N 39 (2) Clock Input
— — ADB_PWDN 36 (3) Power-Down Function Select
Notes to Table 2–11 :
(1) This pin is connected to Multiplexer pin U10.15.
(2) This pin is connected to Multiplexer pin U10.14.
(3) This pin is connected to Jumper pin J6.2.
Table 2–11. A/D Converter Channel B (U2) Pin-Out Information (Part 2 of 2)
HSMC Signal HSMC Pin Device Signal
Device
Pin Number Description