Altera Data Conversion HSMC - Manual (Page 41)

Appendix C: Pin-Out Information for the Cyclone III (3C25) Starter Board C–3
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
131 D/A A bit 3 from Host DA3 HSMC_TX_p13 2.5 V L14
132 D/A B bit 3 from Host DB3 HSMC_RX_p13 2.5 V L13
133 D/A A bit 2 from Host DA2 HSMC_TX_n13 2.5 V L15
134 D/A B bit 2 from Host DB2 HSMC_RX_n13 2.5 V M14
137 D/A A bit 1 from Host DA1 HSMC_TX_p14 2.5 V P17
138 D/A B bit 1 from Host DB1 HSMC_RX_p14 2.5 V R17
139 D/A A bit 0 from Host DA0 HSMC_TX_n14 2.5 V P18
140 D/A B bit 0 from Host DB0 HSMC_RX_n14 2.5 V R18
143 Audio Codec Data In from
Host AIC_DIN HSMC_TX_p15 2.5 V R5
144 Audio Codec Data Out to Host AIC_DOUT HSMC_RX_p15 2.5 V M6
145 Audio Codec L/R In from Host AIC_LRCIN HSMC_TX_n15 2.5 V R4
146 Audio Codec L/R Out to Host AIC_LRCOUT HSMC_RX_n15 2.5 V N6
149 Audio Codec Bclk from Host AIC_BCLK HSMC_TX_p16 2.5 V T17
150 Audio Codec XTI/MCLK from
Host AIC_XCLK HSMC_RX_p16 2.5 V M13
151 Audio Codec SPI Chip Select
from Host AIC_SPI_CS HSMC_TX_n16 2.5 V T18
155 A/D Clock B from Host
Differential P FPGA_CLK_B_P HSMC_CLKOUT_p2 LVDS U18
156 A/D A Data Clock Out to Host ADA_DCO HSMC_CLKIN_p2 2.5 V N17
157 A/D Clock B from Host
Differential N FPGA_CLK_B_N HSMC_CLKOUT_n2 LVDS V18
158 A/D B Data Clock Out to Host ADB_DCO HSMC_CLKIN_n2 2.5 V N18
Table C–1. HSMC Port Interface Pin-Out Information (Part 3 of 3)
Data Conversion HSMC Schematic Development Board Schematic
Board
Reference
(J1) Description
Schematic
Signal Name
Schematic
Signal Name
I/O
Standard
Cyclone III
Pin Number