Configuration, status, and setup elements, A/d converter clock select jumper (j3, j7), Configuration, status, and setup elements –3 – Altera Data Conversion HSMC User Manual

Page 9: A/d converter clock select jumper (j3, j7) –3

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Chapter 2: Board Components and Interfaces

2–3

Configuration, Status, and Setup Elements

© November 2008

Altera Corporation

Data Conversion HSMC Reference Manual

Configuration, Status, and Setup Elements

This section describes configuration, status, and setup elements.

A/D Converter Clock Select Jumper (J3, J7)

Table 2–2

lists the J3 (channel A) and J7 (channel B) jumper settings used to select the

A/D converter clock.

J25 (External Clock Out-p)

J28 (External Clock Out-n)

External clock output SMA
connectors

SMA connectors for a differential clock output

2–7

Components and Interfaces

U1 (Channel A)

U2 (Channel B)

A/D converter

Analog Devices AD9254. 14-bit, 150 MS/s ADC

2–7

J4 (Channel A)

J8 (Channel B)

A/D converter input SMAs

SMAs that drive the A/D converter inputs

2–11

U3 (Channels A and B)

D/A converter

Texas Instruments DAC5672. 14-bit, 175 MS/s
D/A converter

2–11

J12 (Channel A)

J14 (Channel B)

D/A converter output SMAs

SMA outputs for the D/A converters

2–14

U5

Audio CODEC

Texas Instruments TLV320AK23. Stereo Audio CODEC,
96 KHz, with integrated headphone amplifier

2–14

J19

Line-in audio jack

3.5-mm audio connector for line-in

2–15

J20

Line-out audio jack

3.5-mm audio connector for line-out

2–15

J21

Headphone jack

3.5-mm audio connector for headphone

2–15

J42

Mic jack

3.5-mm audio connector for microphone

2–15

J1

HSMC

Expansion connector used to interface with Altera
development boards

2–15

U14

I

2

C EEPROM

ISSI EEPROM IS24C02B, 2 Kbits

2–16

Table 2–1. Data Conversion HSMC Feature Overview (Part 2 of 2)

Board Reference

Name

Description

Page

Table 2–2. A/D Converter Clock Select Jumper (J3, J7) Settings (Part 1 of 2)

Clock Source

Board Reference

Schematic Signal Name

(1)

,

(2), (3)

A/D Converter Clock Select (J3 or J7)

Jumper Setting

FPGA Clock

HSMC Connector

FPGA_CLK_A_P

FPGA_CLK_A_N

Pins 3 and 5

Pins 4 and 6

FPGA Clock

HSMC Connector

FPGA_CLK_B_P

FPGA_CLK_B_N

Pins 1 and 3

Pins 4 and 6

External Clock

External Clock Input SMA

XT_IN_P

XT_IN_N

Pins 3 and 5

Pins 2 and 4

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