Altera Data Conversion HSMC - Manual (Page 19)

Chapter 2: Board Components and Interfaces 2–13
Component Interfaces
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
D/A Converter Clocks
Figure 2–6 shows the components involved in selecting the clock signal to be sent to
the DAC5672 (U3 for channels A and B). J15 (channel A) or J17 (channel B) selects the
D/A clock from the FPGA clock A, the FPGA clock B, or the SMA clock (J26 and J30).
The selected D/A clock passes through a differential to LVDS clock multiplexer (U11
for channel A, U12 for channel B), which provides the clock signal to 2-bit high-speed
differential receiver FIN1028, which in turn outputs clock to the DAC5672 (refer to
“D/A Converter Clock Select Jumper (J15, J17)” on page 2–4 .)
Figure 2–6. D/A Converter Clocking Options
FPGA_CLK_A_P
NO_CLK_P
NO_CLK_N
DAA_CLK_S1
DAA_CLK_S0
PCLK0P
PCLK0N
PCLK1P
PCLK1N
PCLK2P
PCLK2N
PCLK3P
PCLK3N
SEL0
SEL1
VDD
VDD
QP
QN
GND
GND
3.3 V
DAC_CLK_1_N
DAC_CLK_1_P
FPGA_CLK_A_N
FPGA_CLK_A_P
FPGA_CLK_A_N
1
2
3
4 FPGA_CLK_B_P
FPGA_CLK_B_N FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
XT_IN_P
XT_IN_N
9
10
11
12 NO_CLK_P
NO_CLK_N
6
7
13
8
15
14
5
16
C103 C104
0.1µF 1.0nF
ICS854054
U11
FPGA_CLK_A_P
NO_CLK_P
NO_CLK_N
DAB_CLK_S1
DAB_CLK_S0
PCLK0P
PCLK0N
PCLK1P
PCLK1N
PCLK2P
PCLK2N
PCLK3P
PCLK3N
SEL0
SEL1
VDD
VDD
QP
QN
GND
GND
3.3 V
DAC_CLK_2_N
DAC_CLK_2_P
FPGA_CLK_A_N
FPGA_CLK_A_P
FPGA_CLK_A_N
1
2
3
4 FPGA_CLK_B_P
FPGA_CLK_B_N FPGA_CLK_B_P
FPGA_CLK_B_N
XT_IN_P
XT_IN_N
XT_IN_P
XT_IN_N
9
10
11
12 NO_CLK_P
NO_CLK_N
6
7
13
8
15
14
5
16
C105 C106
1.0nF 0.1µF
ICS854054
U12