Altera Data Conversion HSMC - Manual (Page 37)

Appendix B: Pin-Out Information for the Stratix III (3SL150) Development Board B–5
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
115 LVDS TX or CMOS I/O bit 10 DA8 HSMB_TX_N10 LVDS or 2.5 V K5
116 LVDS RX or CMOS I/O bit 10 DB8 HSMB_RX_N10 LVDS or 2.5 V G1
119 LVDS TX or CMOS I/O bit 11 DA7 HSMB_TX_P11 LVDS or 2.5 V J7
120 LVDS RX or CMOS I/O bit 11 DB7 HSMB_RX_P11 LVDS or 2.5 V H4
121 LVDS TX or CMOS I/O bit 11 DA6 HSMB_TX_N11 LVDS or 2.5 V J6
122 LVDS RX or CMOS I/O bit 11 DB6 HSMB_RX_N11 LVDS or 2.5 V H3
125 LVDS TX or CMOS I/O bit 12 DA5 HSMB_TX_P12 LVDS or 2.5 V H6
126 LVDS RX or CMOS I/O bit 12 DB5 HSMB_RX_P12 LVDS or 2.5 V E2
127 LVDS TX or CMOS I/O bit 12 DA4 HSMB_TX_N12 LVDS or 2.5 V H5
128 LVDS RX or CMOS I/O bit 12 DB4 HSMB_RX_N12 LVDS or 2.5 V E1
131 LVDS TX or CMOS I/O bit 13 DA3 HSMB_TX_P13 LVDS or 2.5 V K8
132 LVDS RX or CMOS I/O bit 13 DB3 HSMB_RX_P13 LVDS or 2.5 V C1
133 LVDS TX or CMOS I/O bit 13 DA2 HSMB_TX_N13 LVDS or 2.5 V K7
134 LVDS RX or CMOS I/O bit 13 DB2 HSMB_RX_N13 LVDS or 2.5 V D1
137 LVDS TX or CMOS I/O bit 14 DA1 HSMB_TX_P14 LVDS or 2.5 V L9
138 LVDS RX or CMOS I/O bit 14 DB1 HSMB_RX_P14 LVDS or 2.5 V D3
139 LVDS TX or CMOS I/O bit 14 DA0 HSMB_TX_N14 LVDS or 2.5 V L8
140 LVDS RX or CMOS I/O bit 14 DB0 HSMB_RX_N14 LVDS or 2.5 V D2
143 LVDS TX or CMOS I/O bit 15 AIC_DIN HSMB_TX_P15 LVDS or 2.5 V M10
144 LVDS RX or CMOS I/O bit 15 AIC_DOUT HSMB_RX_P15 LVDS or 2.5 V G5
145 LVDS TX or CMOS I/O bit 15 AIC_LRCIN HSMB_TX_N15 LVDS or 2.5 V M9
146 LVDS RX or CMOS I/O bit 15 AIC_LRCOUT HSMB_RX_N15 LVDS or 2.5 V G4
149 LVDS TX or CMOS I/O bit 16 AIC_BCLK HSMB_TX_P16 LVDS or 2.5 V N11
150 LVDS RX or CMOS I/O bit 16 AIC_XCLK HSMB_RX_P16 LVDS or 2.5 V F4
151 LVDS TX or CMOS I/O bit 16 AIC_SPI_CS HSMB_TX_N16 LVDS or 2.5 V N10
155 LVDS or CMOS clock out FPGA_CLK_B_P HSMB_CLK_OUT_P2 LVDS R12
156 LVDS or CMOS clock in ADA_DCO HSMB_CLK_IN_P2 LVDS U4
157 LVDS or CMOS clock out FPGA_CLK_B_N HSMB_CLK_OUT_N2 2.5 V T11
158 LVDS or CMOS clock in ADB_DCO HSMB_CLK_IN_N2 2.5 V U3
Table B–2. HSMC Port B Interface Pin-Out Information (Part 3 of 3)
Data Conversion HSMC Schematic Development Board Schematic
Board
Reference
(J1) Description
Schematic
Signal Name
Schematic
Signal Name I/O Standard
Stratix III
Pin
Number