Altera Data Conversion HSMC - Manual (Page 20)

2–14 Chapter 2: Board Components and Interfaces
Component Interfaces
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
Table 2–15 provides the differential to LVDS clock multiplexer pin-out details.
D/A Converter Output SMA Connector (J12, J14)
J12 (channel A) and J14 (channel B) are standard through-hole SMA connectors used
to interface the DAC5672 D/A converter output with SMA cables.
Audio CODEC Converter (U5)
The Data Conversion HSMC contains three stereo jack and one mic jack connectors
which provide one stereo output, one stereo input, one amplified stereo headphone
output, and one microphone input. The stereo jacks are driven by a stereo audio
CODEC running at 8 to 96 kHz.
Table 2–16 lists the audio CODEC board reference
and manufacturing information.
Table 2–17 provides the TI TLV320AIC23 audio CODEC pin-out details.
Table 2–15. Differential to LVDS Clock Multiplexer (U11, U12) Pin-Out Information
Schematic Signal
HSMC
Connector
Pin Number Device Signal
Device
Pin Number Description
FPGA_CLK_A_P 95 PCLK0P 1 Non-inverting Differential clock input
FPGA_CLK_A_N 97 PCLK0N 2 Inverting Differential clock input
FPGA_CLK_B_P 155 PCLK1P 3 Non-inverting Differential clock input
FPGA_CLK_B_N 157 PCLK1N 4 Inverting Differential clock input
XT_IN_P 96 PCLK2P 9 Non-inverting Differential clock input
XT_IN_N 98 PCLK2N 10 Inverting Differential clock input
DA(A,B)_CLK_SEL_P — QP 15 Non-inverting Differential Clock Output
DA(A,B)_CLK_SEL_N — QN 14 Inverting Differential Clock Output
Table 2–16. Audio CODEC Converter Component Reference
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U5 Stereo Audio CODEC, 8–96 KHz, with
Integrated Headphone Amplifier Texas Instruments TLV320AIC23 www.ti.com
Table 2–17. Audio CODEC Converter (U5) Pin-Out Information (Part 1 of 2)
HSMC Signal HSMC Pin Device Signal
Device
Pin Number Description
AIC_XCLK 150 XTI/MCLK 25 Crystal or external-clock input. Used for derivation of all
internal clocks on the AIC23B.
AIC_LRCOUT 146 LRCOUT 7 I2S A/D converter-word clock signal. In audio master
mode, the AIC23B generates this framing signal and sends
it to the DSP. In audio slave mode, the signal is generated
by the DSP.
AIC_LRCIN 145 LRCIN 5 I2S D/A converter-word clock signal. In audio master
mode, the AIC23B generates this framing signal and sends
it to the DSP. In audio slave mode, the signal is generated
by the DSP.