Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 172)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 172
0x40000
...
0x40FFF Gr8TrmDatMem0
...
Gr8TrmDatMem102
3 Holds the transmit data for 672 Gr8 via Sonet/Sdh and 48 Gr8
channels via Exar T1 Framers.
The data is copied from host memory by means of host DMA in
9ms intervals, the host is triggered by interrupt (see General
Registers, Component Event Register).
The actual memory has the double of the needed size, always
one half is visible to the SW during an interval, the other half is
accessed by HW. In the next interval the two memory halves
are interchanged, thus decoupling SW from HW ensuring
enough processing time for SW.
The cells contain the Transmit Concentrator Field and Transmit
Maintenance., Alarm, Protection Switch Fields of the channels.
The cells 0...767 are prepared by Hw to transmit data to
Pmc8310 Sonet/Sdh Framers. A respective Tsi connection is
needed for every used channel.
The cells 768...1023 are prepared by Hw to transmit data to
Xrt86 Framers. The channels can only be used in groups of four.
The channel with the greatest number (e.g. 771 in group
768..771) must be switched by the Tsi to the respective Hmvip
link channel 0 of a E1/T1 framer.
They may be mapped as following:
The cells 0..335 match to the SBI interface 0 to PMC8310 chip
0, 336 to 671 or SBI interface 1 to PMC8310 chip 1.
Cell 0,4,8,... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 0, channel 0,1,2,...
Cell 1,5,9, ... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 1, channel 0,1,2,...
Cell 2,6,10, ... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 2, channel 0,1,2,...
Cell 3,7,11, ... match to the SBI interface 0 (PMC8310 chip 0),
subsystem 3, channel 0,1,2,
...
Cell 33…6,340,344,... match to the SBI interface 1 (PMC8310
chip 1), subsystem 0, channel 0,1,2,
Cell 337,341,345, ... match to the SBI interface 1 (PMC8310
chip 1), subsystem 1, channel 0,1,2,
Cell 338,342,346, ... match to the SBI interface 1 (PMC8310
chip 1), subsystem 2, channel 0,1,2,
Table 9-5 RTM FPGA Address map Overview (continued)