Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 210)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 210
9.5.2.6.3 Test Pattern Generator Control Register
Addresses:
0x1083, TstPatGenCtrlReg0
0x1093, TstPatGenCtrlReg1
Width: 8 bit
This registers controls test pattern transmission
9.5.2.7 TSI Interior/Exterior Test Pattern Comparator Block (TsiTstPatCmpBlk)
Resets:
Bit Acronym Type
Description
Default
Pwr Soft
7...
6 - - reserved undef - -
5 TstPatGenContErrPrv
k RW 0b1: TstPatGenContErrPrvk, errors are
inserted continuously 0b0 X X
4 TstPatGenSingleErrPr
vk RW 0b1: TstPatGenSingleErrPrvk, one error
is inserted when the bit changes from 0
to 1 0b0 X X
3 TstPatGenBitstInvert RW 0b1: TstPatGenBitstrInvert, selects that
test pattern bitstream is sent inverted
0b0: TstPatGenBitstrNotInvert, selects
that test pattern bitstream is sent not
inverted 0b0 X X
2 - - reserved undef - -
1 TstPatGenPatSel RW Specifies the pattern source:
0b1: TstPatGenPatPrbs, selects the
PRBS pattern
0b0: TstPatGenPatStatic, selects the
static pattern 0b0 X X
0 TstPatGenTxPatEn RW 0b1: TstPatGenTxPatEn, enables the
pattern insertion 0b0 X X