Tsi fpga, 25spi 1 bus access monitor address register – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 256
TSI FPGA
ARTM-831X Installation and Use (6806800M76E)
256
Width: 8 bit
This register resets the timeout flag in the respective monitor and address registers
9.5.2.11.25Spi 1 Bus Access Monitor Address Register
Address:
0x14A4, Spi1BusAccessTimeoutAddrReg
Width: 32 bit
This register stores the address of the last timedout access to the Spi 1 Bus
Bit
Acronym
Type
Description
Default
Pwr
Soft
7...1
-
-
reserved
undef
-
-
0
Spi1BusAccessTimeoutReset
RW
0b1:
Spi1BusAccessTimeoutRes
et, The timeout flag in the
monitor register is reset.
0b0
X
X
Bit
Acronym
Type
Description
Default
Pwr
Soft
31
Spi1BusAccessedDirection
R
0b1: Spi1BusAccessWrite,
An address at Spi 1 Bus has
been written with timeout
0b0: Spi1BusAccessRead,
An address at Spi 1 Bus has
been read with timeout
0b0
F
F
30...24
-
-
reserved
undef
-
-
23...20
Spi1BusAccessedSelects
R
The selects recorded
during the last timedout
access to the Spi 1 bus
0x0
F
F
19
-
-
reserved
undef
-
-
18...0
Spi1BusAccessedAddress
R
The address recorded
during the last timedout
access to Spi 1 bus
0x0
F
F