Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 258)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 258
This register stores the address of the last timedout access to the Spi 2 Bus
9.5.2.12 General Test Registers (GenTestRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
General Test Registers
9.5.2.12.1 Soft Error Fault Insertion Register
Address:
0x1500, SoftErrFltInsrtReg
Width: 32 bit
Bit Acronym Type Description Default Pwr Soft
31 Spi2BusAccessedDirection R 0b1: Spi2BusAccessWrite,
An address at Spi 2 Bus has
been written with timeout
0b0: Spi2BusAccessRead,
An address at Spi 2 Bus has
been read with timeout 0b0 F F
30...24 - - reserved undef - -
23...20 Spi2BusAccessedSelects R The selects recorded during
the last timedout access to
Spi 2 bus 0x0 F F
19 - - reserved undef - -
18...0 Spi2BusAccessedAddress R The address recorded
during the last timedout
access to Spi 2 bus 0x0 F F