Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 218)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 218
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
9.5.2.8.4 Supplemental Test Pattern, CRC and Disparity Generator Control Register
Addresses:
0x1104, SupplTstPatCrcDispGenCtrlReg0
0x1144, SupplTstPatCrcDispGenCtrlReg1
0x1184, SupplTstPatCrcDispGenCtrlReg2
Width: 8 bit
This registers control the test pattern, CRC and Disparity transmission.
Reg0 is for Serdes-connection to the BaseBoard, Reg1 to DMC1 and Reg2 to DMC2.
Bit Acronym Type
Description
Default
Pwr Soft
15..
.0 SupplTstPatTrmData RW Test pattern for transmission via the
supplementary channel towards the
serial interface 0b0 X X
Bit Acronym Type
Description
Default
Pwr Soft
7...
6 - - reserved undef - -
5 SupplTstPatGenCont
ErrPrvk RW 0b1: SupplTstPatGenContErrPrvk,
errors are inserted continuously 0b0 X X
4 SupplTstPatGenSingl
eErrPrvk RW 0b1: SupplTstPatGenSingleErrPrvk,
one error is inserted when the bit
changes from 0 to 1 0b0 X X