Artesyn COMX-P2020 BSP User Guide (July 2014) - Manual (Page 44)

U-boot Deployment
COMX-P2020 BSP User Guide (6806800L84B) 44
5.3.4
Set the switch as: SW1[1] = OFF, SW1[2] = ON, SW2[1] = ON, SW2[2] = OFF, and power on the
board.
Normally, you can see the following information from the serial terminal as below:
U-Boot 2009.11-V100R00 (Dec 09 2010 - 14:39:42)
CPU0: P2020E, Version: 2.0, (0x80ea0020)
Core: E500, Version: 5.0, (0x80211050)
Clock Configuration:
CPU0:1200 MHz, CPU1:1200 MHz,
CCB:600 MHz,
DDR:333.333 MHz (666.667 MT/s data rate) (Asynchronous), LBC:37.500
MHz
L1: D-cache 32 kB enabled
I-cache 32 kB enabled
I2C: ready
SPI: ready
DRAM: 2 GB
L2: 512 KB enabled
MMC: FSL_ESDHC: 0
EEPROM: NXID v0
EEPROM: COMX
PCIE3 connected to Slot0 as Root Complex (base addr ffe08000)
PCIE3 on bus 00 - 00
PCIE2 connected to Slot 1 as Root Complex (base addr ffe09000)