Measurement Computing DaqScan 2000 Series - Manual (Page 69)

Specifications are subject to change without notice.
DaqScan/2000 Series 898095 Specifications 11-3
2. Single-Channel Analog Software Trigger.
Any analog input channel, including any of the analog expansion channels, can be selected as the software
trigger channel. If the trigger channel involves a calculation, such as with temperature, then the driver
automatically compensates for the delay required to calculate the reading, resulting in a maximum latency of
one scan period.
Input Signal Range: Anywhere within the range of the selected trigger channel
Trigger Level: Programmable, 16-bit resolution, including “window triggering”
Hysteresis: Programmable, 16-bit resolution
Latency: One scan period max.
3. Single-Channel Digital Trigger: A separate digital input is provided for digital triggering.
Input Signal Range: -15V to +15V max.
Trigger Level: TTL
Minimum Pulse Width: 50 ns high, 50 ns low
Latency: 5
µs max.
4. Digital Pattern Triggering: 8 or 16-bit pattern triggering on any digital input. Programmable for trigger on
equal, above, below, or within or outside of a window. Individual bits can be masked for “don’t care”
condition.
Latency: One scan period maximum.
5. Counter/Totalizer Triggering: Counter/totalizer inputs can trigger an acquisition. User can select to trigger
on a frequency or on total counts that are equal, above, below, or within/outside of a window.
Latency: One scan period maximum.
6. Software Triggering: Trigger can be initiated under program control.
Analog Outputs (DaqScan/2001 and DaqScan/2004 only)
For DaqScan/2001 and DaqScan/2004, four analog output channels are updated synchronously relative to
scanned inputs, and clocked from either an internal onboard clock, or an external clock source. Analog outputs
can also be updated asynchronously, independent of any other scanning in the system.
Channels: 4 DAC channels; numbered 0, 1, 2, and 3
Connectors: pins 31 (DAC3), 32 (DAC2), 33 (DAC1), and 34 (DAC0) on the P3 DB37 connector
Resolution: 16 bits
Data Buffer: 256 Ksample
Output voltage range:
±10 V
Output current:
±10 mA
Offset error:
±0.0045 V maximum
Gain error:
±0.01%
Digital Feedthru: 50 mV when updated
Update rate: 100 kHz maximum, 1.5 Hz minimum (no minimum with external clock)
Settling Time: 10
µs maximum to 1 LSB for full-scale step
Clock Sources: 4 programmable
1. Onboard D/A clock, independent of scanning input clock
2. Onboard scanning input clock
3. External D/A input clock, independent of external scanning input clock
4. External scanning input clock; available via screw-terminal on front panel removable block