Sundance SMT395Q - Manual (Page 11)

Version 1.0.7 Page 11 of 31 SMT395Q User Manual
CECTL1B = 0xFFF50D13;
CECTL2B = 0xFFFFFF23;
CECTL3B = 0x105FFF23;
SDEXTA = 0x53227000;
SDRAM
DSP_A has access to 128MB of SDRAM. DSP_B, C & D have 64MB. The SDRAM operates
at the EMIF clock speed. It is typically 120MHz for the SMT395Q.
DSP_B, C & D have 64MB at address 0x80000000.
DSP_A has 128MB with 64MB at address 0x80000000, and 64MB at 0x90000000.
FLASH
An 8MB Flash ROM memory is provided with direct access by DSP_A. This device contains
boot code for the DSP and the configuration data for the FPGA.
This is a 16-bit wide device.
The flash device can be re-programmed by the DSP at any time. There is a software
protection mechanism to stop most errant applications from destroying the device’s contents.
Note that the flash memory is connected as a 16-bit device, but during a C6x boot (internal
function of the C6x) only the bottom 8 bits are used.
As the C60 only provides 20 address lines on its EMIF_B, two GPIO lines (9 and 10) are
used to access this device. So the device should be seen as divided in 4x 2MB pages.
FLASH Paging
Selecting the visible flash memory page (4 pages of 2Mbytes) involves setting up the GPIO
registers bit 9 and 10. Make sure that the setup of the other GPIO is kept untouched as they
are used for external interrupt and leds.