Avago Technologies LSI53C1000R - Manual (Page 118)

4-6 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
These bits are read only and indicate the slowest time
that a device asserts DEVSEL/ for any bus command
except Configuration Read and Configuration Write. The
LSI53C1000R only supports medium DEVSEL/ timing.
DPR Data Parity Error Reported 8
This bit is set when the following conditions are met:
•
The bus agent asserts PERR/ itself or observes
PERR/ asserted and;
•
The agent setting this bit acted as the bus master for
the errant operation and;
•
The Parity Error Response bit in the Command
register is set.
FBBC Fast Back to Back Capable 7
This bit is zero.
R Reserved 6
66C 66 MHz Capable 5
When set, this bit indicates that the LSI53C1000R is
capable of 66 MHz PCI operation. This bit is controlled
by the ENABLE66 pin, which has a static pull-up.
NC New Capabilities 4
This bit is set to indicate a list of extended capabilities
such as PCI Power Management. This bit is read only.
R Reserved [3:0]
Register: 0x08
Revision ID (RID)
Read Only
RID Revision ID [7:0]
This register indicates the current revision level of the
device.
7 0
RID
x x x x x x x x