Avago Technologies LSI53C1000R User Manual
Page 175
SCSI Registers
4-63
Version 2.2
Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
end-of-transfer cleanup and alignment, even if less than
a full burst of transfers is performed. The LSI53C1000R
inserts a “fairness delay” of four CLKs between burst
transfers (set in BL[2:0]) during normal operation. The
fairness delay is not inserted during PCI retry cycles. This
gives the CPU and other bus master devices the
opportunity to access the PCI bus between bursts.
SIOM
Source I/O-Memory Enable
5
This bit is defined as an I/O Memory Enable bit for the
source address of a Memory Move or Block Move
Command. If this bit is set, then the source address is in
I/O space; if cleared, the source address is in
memory space.
This function is useful for register-to-memory operations
using the Memory Move instruction when an
LSI53C1000R is I/O mapped. Bits 4 and 5 of the
register determine the
configuration status of the LSI53C1000R.
DIOM
Destination I/O-Memory Enable
4
This bit is defined as an I/O Memory Enable bit for the
destination address of a Memory Move or Block Move
Command. If this bit is set, then the destination address
is in I/O space; if cleared, the destination address is in
memory space.
BL2
(CTEST5 Bit 2)
BL1
BL0
Number
of 64
-
Bit
Transfers
Number
of 32
-
Bit
Transfers
0
0
0
4
8
0
0
1
4
8
0
1
0
8
16
0
1
1
16
32
1
0
0
32
64
1
0
1
64
128
1
1
0
64
128
1
1
1
Reserved
Reserved