Avago Technologies LSI53C1000R - Manual (Page 331)

PCI and External Memory Interface Timing Diagrams 6-49
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.27 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Read Cycle
Figure 6.27 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Read
Cycle (Cont.)
CLK
(Driven by System)
Data Driven by Memory)
1 2 3 4 5 6 7 8 9 10
MAD
(Addr driven by LSI53C1000R;
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
t
13
t
11 t
12
t
15
t
14
t
16
CLK
(Driven by System)
Data Driven by Memory)
11 12 13 14 15 16 17 18 19 20
MAD
(Addr driven by LSI53C1000R;
MAS1/
(Driven by LSI53C1000R)
MAS0/
(Driven by LSI53C1000R)
MCE/
(Driven by LSI53C1000R)
MOE/
(Driven by LSI53C1000R)
MWE/
(Driven by LSI53C1000R)
t
15
21
Read
Data
t
19
t
17
t
14
t
16
Valid
t
18