Avago Technologies LSI53C1000R - Manual (Page 236)

4-124 Registers
Version 2.2 Copyright © 2000–2003 by LSI Logic Corporation. All rights reserved.
Registers: 0xF0–0xF1
DMA FIFO Byte Count (DFBC)
Read Only
DFBC DMA FIFO Byte Count [15:0]
This 16-bit read only register contains the actual number
of bytes contained in the DMA FIFO. This register is not
stable while data is actually being transferred. This
register can be used during error recovery.
Registers: 0xF2–0xF3
Reserved
This register is reserved.
Registers: 0xF4–0xFF
Reserved
This register is reserved.
15 0
DFBC
x x x x x x x x x x x x x x x x
15 0
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 0
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0