Avago Technologies LSI53C895A User Manual
Avago Technologies Hardware
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Table of contents
Document Outline
- Chapter1 General Description
- Chapter2 Functional Description
- Figure2.1 LSI53C895A Block Diagram
- 2.1 PCI Functional Description
- 2.1.1 PCI Addressing
- 2.1.2 PCI Bus Commands and Functions Supported
- Table 2.1 PCI Bus Commands and Encoding Types for the LSI53C895A
- 2.1.2.1 Interrupt Acknowledge Command
- 2.1.2.2 Special Cycle Command
- 2.1.2.3 I/O Read Command
- 2.1.2.4 I/O Write Command
- 2.1.2.5 Reserved Command
- 2.1.2.6 Memory Read Command
- 2.1.2.7 Memory Write Command
- 2.1.2.8 Configuration Read Command
- 2.1.2.9 Configuration Write Command
- 2.1.2.10 Memory Read Multiple Command
- 2.1.2.11 Dual Address Cycle (DAC) Command
- 2.1.2.12 Memory Read Line Command
- 2.1.2.13 Memory Write and Invalidate Command
- 2.1.3 PCI Cache Mode
- 2.2 SCSI Functional Description
- 2.2.1 SCRIPTS Processor
- 2.2.2 Internal SCRIPTS RAM
- 2.2.3 64-Bit Addressing in SCRIPTS
- 2.2.4 Hardware Control of SCSI Activity LED
- 2.2.5 Designing an Ultra2 SCSI System
- 2.2.6 Prefetching SCRIPTS Instructions
- 2.2.7 Opcode Fetch Burst Capability
- 2.2.8 Load and Store Instructions
- 2.2.9 JTAG Boundary Scan Testing
- 2.2.10 SCSI Loopback Mode
- 2.2.11 Parity Options
- 2.2.12 DMA FIFO
- 2.2.13 SCSI Bus Interface
- 2.2.14 Select/Reselect During Selection/Reselection
- 2.2.15 Synchronous Operation
- 2.2.16 Interrupt Handling
- 2.2.17 Interrupt Routing
- 2.2.18 Chained Block Moves
- 2.3 Parallel ROM Interface
- 2.4 Serial EEPROM Interface
- 2.5 Alternative SSVID/SSID Loading Mechanism
- 2.6 Power Management
- Chapter3 Signal Descriptions
- 3.1 LSI53C895A Functional Signal Grouping
- 3.2 Signal Descriptions
- 3.3 PCI Bus Interface Signals
- 3.4 SCSI Bus Interface Signals
- 3.5 Flash ROM and Memory Interface Signals
- 3.6 Test Interface Signals
- 3.7 Power and Ground Signals
- 3.8 MAD Bus Programming
- Chapter4 Registers
- Chapter5 SCSI SCRIPTS Instruction Set
- Chapter6 Electrical Specifications
- 6.1 DC Characteristics
- Table 6.1 Absolute Maximum Stress Ratings
- Table 6.2 Operating Conditions
- Table 6.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/...
- Figure6.1 LVD Driver
- Table 6.4 LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SI...
- Figure6.2 LVD Receiver
- Table 6.5 DIFFSENS SCSI Signal
- Table 6.6 Input Capacitance
- Table 6.7 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/, MWE/
- Table 6.8 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/, GPIO[2:8]
- Table 6.9 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/...
- Table 6.10 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI, TEST_HSC, TEST_RST, TMS, TRST/
- Table 6.11 Output Signal—TDO
- Table 6.12 Output Signals—ALT_IRQ/, IRQ/, MAC/_TESTOUT, REQ/
- Table 6.13 Output Signal—SERR/
- 6.2 TolerANT Technology Electrical Characteristics
- Table 6.14 TolerANT Technology Electrical Characteristics for SE SCSI Signals
- Figure6.3 Rise and Fall Time Test Condition
- Figure6.4 SCSI Input Filtering
- Figure6.5 Hysteresis of SCSI Receivers
- Figure6.6 Input Current as a Function of Input Voltage
- Figure6.7 Output Current as a Function of Output Voltage
- 6.3 AC Characteristics
- 6.4 PCI and External Memory Interface Timing Diagrams
- 6.4.1 Target Timing
- Table 6.18 PCI Configuration Register Read
- Figure6.11 PCI Configuration Register Read
- Table 6.19 PCI Configuration Register Write
- Figure6.12 PCI Configuration Register Write
- Table 6.20 32-Bit Operating Register/SCRIPTS RAM Read
- Figure6.13 32-Bit Operating Register/SCRIPTS RAM Read
- Table 6.21 64-Bit Address Operating Register/SCRIPTS RAM Read
- Figure6.14 64-Bit Address Operating Register/SCRIPTS RAM Read
- Table 6.22 32-Bit Operating Register/SCRIPTS RAM Write
- Figure6.15 32-Bit Operating Register/SCRIPTS RAM Write
- Table 6.23 64-Bit Address Operating Register/SCRIPTS RAM Write
- Figure6.16 64-Bit Address Operating Register/SCRIPTS RAM Write
- 6.4.2 Initiator Timing
- Table 6.24 Nonburst Opcode Fetch, 32-Bit Address and Data
- Figure6.17 Nonburst Opcode Fetch, 32-Bit Address and Data
- Table 6.25 Burst Opcode Fetch, 32-Bit Address and Data
- Figure6.18 Burst Opcode Fetch, 32-Bit Address and Data
- Table 6.26 Back to Back Read, 32-Bit Address and Data
- Figure6.19 Back to Back Read, 32-Bit Address and Data
- Table 6.27 Back to Back Write, 32-Bit Address and Data
- Figure6.20 Back to Back Write, 32-Bit Address and Data
- Table 6.28 Burst Read, 32-Bit Address and Data
- Figure6.21 Burst Read, 32-Bit Address and Data
- Table 6.29 Burst Read, 64-Bit Address and Data
- Figure6.22 Burst Read, 64-Bit Address and Data
- Table 6.30 Burst Write, 32-Bit Address and Data
- Figure6.23 Burst Write, 32-Bit Address and Data
- Table 6.31 Burst Write, 64-Bit Address and 32-Bit Data
- Figure6.24 Burst Write, 64-Bit Address and 32-Bit Data
- 6.4.3 External Memory Timing
- Table 6.32 External Memory Read
- Figure6.25 External Memory Read
- Table 6.33 External Memory Write
- Figure6.26 External Memory Write
- Table 6.34 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
- Figure6.27 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Read Cycle
- Table 6.35 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
- Figure6.28 Normal/Fast Memory (³ 128 Kbytes) Single Byte Access Write Cycle
- Figure6.29 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Read Cycle
- Figure6.30 Normal/Fast Memory (³ 128 Kbytes) Multiple Byte Access Write Cycle
- Table 6.36 Slow Memory (£ 128 Kbytes) Read Cycle
- Figure6.31 Slow Memory (£ 128 Kbytes) Read Cycle
- Table 6.37 Slow Memory (£ 128 Kbytes) Write Cycle
- Figure6.32 Slow Memory (£ 128 Kbytes) Write Cycle
- Table 6.38 £ 64 Kbytes ROM Read Cycle
- Figure6.33 £ 64 Kbytes ROM Read Cycle
- Table 6.39 £ 64 Kbyte ROM Write Cycle
- Figure6.34 £ 64 Kbyte ROM Write Cycle
- 6.4.1 Target Timing
- 6.5 SCSI Timing Diagrams
- Table 6.40 Initiator Asynchronous Send
- Figure6.35 Initiator Asynchronous Send
- Table 6.41 Initiator Asynchronous Receive
- Figure6.36 Initiator Asynchronous Receive
- Table 6.42 Target Asynchronous Send
- Figure6.37 Target Asynchronous Send
- Table 6.43 Target Asynchronous Receive
- Figure6.38 Target Asynchronous Receive
- Table 6.44 SCSI-1 Transfers (SE 5.0 Mbytes)
- Table 6.45 SCSI-1 Transfers (Differential 4.17 Mbytes)
- Table 6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
- Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes (16-Bit Transfers) ...
- Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers...
- Table 6.49 Ultra SCSI High Voltage Differential Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 M...
- Table 6.50 Ultra2 SCSI Transfers 40.0 Mbytes (8-Bit Transfers) or 80.0 Mbytes (16-Bit Transfers) ...
- Figure6.39 Initiator and Target Synchronous Transfer
- 6.6 Package Diagrams
- 6.1 DC Characteristics
- AppendixA Register Summary
- AppendixB External Memory Interface Diagram Examples
- Index
- Customer Feedback