Avago Technologies LSI53C895A - Manual (Page 49)

SCSI Functional Description 2-23
Step 1. Set the SCLK Quadrupler Enable bit ( SCSI Test One
(STEST1) , bit 3).
Step 2. Poll bit 5 of the SCSI Test Four (STEST4) register. The
LSI53C895A sets this bit as soon as it locks in the 160 MHz
frequency. The frequency lockup takes approximately
100 microseconds.
Step 3. Halt the SCSI clock by setting the Halt SCSI Clock bit ( SCSI
Test Three (STEST3) , bit 5).
Step 4. Set the clock conversion factor using the SCF and CCF fields
in the
SCSI Control Three (SCNTL3) register.
Step 5. Set the SCLK Quadrupler Select bit ( SCSI Test One (STEST1) ,
bit 2).
Step 6. Clear the Halt SCSI Clock bit.
2.2.6 Prefetching SCRIPTS Instructions
When enabled by setting the Prefetch Enable bit (bit 5) in the DMA
Control (DCNTL) register, the prefetch logic in the LSI53C895A fetches
8 Dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform, based on the burst length as
determined by the values in the
DMA Mode (DMODE) register. If the unit
cannot perform bursts of at least four Dwords, it disables itself. While the
chip is prefetching SCRIPTS instructions, it will use PCI cache
commands Memory Read Line, and Memory Read Multiple, if PCI
caching is enabled.
Note: This feature is only useful if fetching SCRIPTS instructions
from main memory. Due to the short access time of
SCRIPTS RAM, prefetching is not necessary when fetching
instructions from this memory.
The LSI53C895A may flush the contents of the prefetch unit under
certain conditions, listed below, to ensure that the chip always operates
from the most current version of the SCRIPTS instruction. When one of
these conditions apply, the contents of the prefetch unit are automatically
flushed.
•
On every Memory Move instruction. The Memory Move instruction is
often used to place modified code directly into memory. To make
sure that the chip executes all recent modifications, the prefetch unit