Avago Technologies LSI53C895A - Manual (Page 354)

IX-8 Index
power (Cont.)
state D0 2-61
state D1 2-61
state D2 2-62
state D3 2-62
power state (PWS[1:0]) 4-17
prefetch
enable (PFEN) 4-72
flush 2-24
flush (PFF) 4-71
SCRIPTS instructions 2-23
pull-ups, internal, conditions 3-3
R
RAM, see also SCRIPTS
RAM 2-20
RBIAS 3-17
read
line 2-11
function 2-7
modify-write cycles 5-23
multiple 2-7
multiple with read line enabled 2-7
write instructions 5-22
write system memory from SCRIPTS 5-34
read/write
instructions 5-22 , 5-24
system memory from SCRIPTS 5-34
received
master abort (from master) (RMA) 4-5
target abort (from master) (RTA) 4-5
register
address 5-37
address - A[6:0] 5-23
registers 2-43
relative 5-19
relative addressing mode 5-17 , 5-29
remaining byte count (RBC) 4-109
REQ/ 3-8
request 3-8
reselect 2-19
during reselection 2-39
instruction 5-14
reselected (RSL) 4-75 , 4-78
reserved 4-4 , 4-6 , 4-10 , 4-13 , 4-16 , 4-17 , 4-23 , 4-31 , 4-36 , 4-39 ,
4-41 , 4-52 , 4-70 , 4-76 , 4-77 , 4-80 , 4-87 , 4-91 , 4-97 , 4-99 ,
4-100 , 4-102 , 4-107 , 4-112 , 4-113
reserved command 2-5
reset 3-4
input 6-13
SCSI offset (ROF) 4-92
response ID one (RESPID1) 4-88
response ID zero (RESPID0) 4-88
return instruction 5-27
revision ID (RID) 4-7
ROM
pin 2-56
RST/ 3-4
S
SACK 2-48
SACK+- 3-13
SACK/ status (ACK) 4-40
SACK2+- 3-13
SACs 2-21
SATN/ status (ATN) 4-40
SATNM+- 3-13
SBSY/ status (BSY) 4-40
SC_D+- 3-13
SC_D/ status (C_D) 4-40
SCLK 3-11
(SCLK) 4-90
quadrupler enable (QEN) 4-91
quadrupler select (QSEL) 4-91
SCNTL0 2-27
SCNTL1 2-26 , 2-27
SCNTL3 2-41 , 2-42
scratch
byte register (SBR) 4-71
register A (SCRATCHA) 4-67
register B (SCRATCHB) 4-103
registers C–R (SCRATCHC–SCRATCHR) 4-103
script fetch selector (SFS) 4-105
SCRIPTS
instruction 2-53
interrupt instruction received (SIR) 4-41 , 4-70
processor 2-19
internal RAM for instruction storage 2-20
performance 2-19
RAM 2-3 , 2-20
running (SRUN) 4-52
SCRIPTS (SCPTS) 4-83
SCSI
ATN condition - target mode (M/A) 4-74
bit mode change (SBMC) 4-80
bus control lines (SBCL) 4-39
bus data lines (SBDL) 4-101
bus interface 2-34
bus mode change (SBMC) 4-76
byte count (SBC) 4-112
C_D/ signal (C_D) 4-46
chip ID (SCID) 4-31
clock 3-11
control 3-13
control enable (SCE) 4-91
control one (SCNTL1) 4-24
control three (SCNTL3) 4-29
control two (SCNTL2) 4-27
control zero (SCNTL0) 4-21
data high impedance (ZSD) 4-60
destination ID (SDID) 4-36
disconnect unexpected (SDU) 4-27
encoded destination ID 5-20
FIFO test read (STR) 4-94
FIFO test write (STW) 4-95
first byte received (SFBR) 4-37
functional description 2-18
GPIO signals 3-10
gross error (SGE) 4-75 , 4-78
I_O/ signal (I/O) 4-46
input data latch (SIDL) 4-96
instructions
block move 5-5
I/O 5-13
read/write 5-22
interface signals 3-11
interrupt enable one (SIEN1) 4-76
interrupt enable zero (SIEN0) 4-74
interrupt pending (SIP) 4-51
interrupt status one (SIST1) 4-80