Avago Technologies LSI53C895A - Manual (Page 192)

4-84 Registers
Register: 0x47
General Purpose Pin Control Zero (GPCNTL0)
Read/Write
This register is used to determine if the pins controlled by the General
Purpose (GPREG0) register are inputs or outputs. Bits [4:0] in GPCNTL0
correspond to bits [4:0] in the GPREG0 register. When the bits are
enabled as inputs, internal pull-downs are enabled for GPIO[4:2] and
internal pull-ups are enabled for GPIO[1:0].
The data written to each bit of the GPREG0 register is output to the
appropriate GPIO pin if it is set to the output mode in the GPCNTL0
register.
ME Master Enable 7
The internal bus master signal is presented on GPIO1 if
this bit is set, regardless of the state of bit 1 (GPIO1).
FE Fetch Enable 6
The internal opcode fetch signal is presented on GPIO0
if this bit is set, regardless of the state of bit 0 (GPIO0).
LEDC LED_CNTL 5
The internal connected signal (bit 3 of the Interrupt Status
Zero (ISTAT0) register) will be presented on GPIO0 if this
bit is set and bit 6 of GPCNTL0 is cleared and the chip
is not in progress of performing an EEPROM
autodownload regardless of the state of bit 0 (GPIO0).
This provides a hardware solution to driving a SCSI
activity LED in many implementations of LSI Logic SCSI
chips.
GPIO GPIO Enable [4:2]
General purpose control, corresponding to bits [4:2] in
the GPREG0 register and pins GPIO[4:2]. GPIO4 powers
up as a general purpose output, and GPIO[3:2] power-up
as general purpose inputs.
7 6 5 4 2 1 0
ME FE LEDC GPIO GPIO
0 0 0 0 1 1 1 1