Power management control/status (pmcsr) – Avago Technologies LSI53C895A User Manual
Page 125
PCI Configuration Registers
4-17
Registers: 0x44–0x45
Power Management Control/Status (PMCSR)
Read/Write
PST
PME Status
15
The LSI53C895A always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
DSCL
Data_Scale
[14:13]
The LSI53C895A does not support the data register.
Therefore, these two bits are always cleared.
DSLT
Data_Select
[12:9]
The LSI53C895A does not support the data register.
Therefore, these four bits are always cleared.
PEN
PME_Enable
8
The LSI53C895A always returns a zero for this bit to
indicate that PME assertion is disabled.
R
Reserved
[7:2]
PWS[1:0]
Power State
[1:0]
Bits [1:0] are used to determine the current power state
of the LSI53C895A. They are used to place the
LSI53C895A in a new power state. Power states are
defined as:
See
Section 2.6, “Power Management,”
in
for
descriptions of the Power Management States.
15
14 13 12
9
8
7
2
1
0
PST DSCL
DSLT
PEN
R
PWS[1:0]
0
0
0
0
0
0
0
0
x
x
x
x
x
x
0
0
0b00
D0
0b01
D1
0b10
D2
0b11
D3hot