Avago Technologies LSI53C895A - Manual (Page 112)

4-4 Registers
R Reserved [15:9]
SE SERR/ Enable 8
This bit enables the SERR/ driver. SERR/ is disabled
when this bit is cleared. The default value of this bit is
zero. This bit and bit 6 must be set to report address
parity errors.
R Reserved 7
EPER Enable Parity Error Response 6
This bit allows the LSI53C895A to detect parity errors on
the PCI bus and report these errors to the system. Only
data parity checking is enabled and disabled with this bit.
The LSI53C895A always generates parity for the PCI
bus.
R Reserved 5
WIE Write and Invalidate Enable 4
This bit allows the LSI53C895A to generate write and
invalidate commands on the PCI bus. The WIE bit in the
DMA Control (DCNTL) register must also be set for the
device to generate Write and Invalidate commands.
R Reserved 3
EBM Enable Bus Mastering 2
This bit controls the ability of the LSI53C895A to act as
a master on the PCI bus. A value of zero disables this
device from generating PCI bus master accesses. A
value of one allows the LSI53C895A to behave as a bus
master. The device must be a bus master in order to fetch
SCRIPTS instructions and transfer data.
EMS Enable Memory Space 1
This bit controls the ability of the LSI53C895A to respond
to Memory space accesses. A value of zero disables the
device response. A value of one allows the LSI53C895A
to respond to Memory Space accesses at the address
range specified by
Base Address Register One (MEM-
ORY) and Base Address Register Two (SCRIPTS RAM)
registers in the PCI configuration space.