Avago Technologies LSI53C895A User Manual
Page 180
4-72
Registers
PFEN
Prefetch Enable
5
Setting this bit enables an 8-Dword SCRIPTS instruction
prefetch unit. The prefetch unit, when enabled, will fetch
8 Dwords of instructions and instruction operands in
bursts of 4 or 8 Dwords. Prefetching instructions allows
the LSI53C895A to make more efficient use of the
system PCI bus, thus improving overall system
performance. The unit will flush whenever the PFF bit is
set, as well as on all transfer control instructions when
the transfer conditions are met, on every write to the
, on every regular MMOV
instruction, and when any interrupt is generated. The unit
automatically determines the maximum burst size that it
is capable of performing based on the burst length as
determined by the values in the
register. If the burst threshold is set to 8 Dwords the
prefetch unit will fetch instructions in two bursts of 4
Dwords. If the burst threshold is set to 16 Dwords or
greater the prefetch unit will fetch instructions in one burst
of 8 Dwords. Burst thresholds of less than 8 Dwords will
cause the prefetch unit to be disabled. PCI Cache
commands (Read Line and Read Multiple) will be issued
appropriately if PCI caching is enabled. Prefetching from
SCRIPTS RAM is not supported and is unnecessary due
to the speed of the fetches. When fetching from
SCRIPTS RAM the setting of this bit will have no effect
on the fetch mechanism from SCRIPTS RAM.
SSM
Single Step Mode
4
Setting this bit causes the LSI53C895A to stop after
executing each SCRIPTS instruction, and generate a
single step interrupt. When this bit is cleared the
LSI53C895A does not stop after each instruction. It
continues fetching and executing instructions until an
interrupt condition occurs. For normal SCSI SCRIPTS
operation, keep this bit clear. To restart the LSI53C895A
after it generates a SCRIPTS Step interrupt, read the
Interrupt Status Zero (ISTAT0)
,
and
registers to recognize
and clear the interrupt. Then set the START DMA bit in
this register.