See figure 23), See figure 24) – Motorola TMS320C6711D User Manual
Page 69
TMS320C6711D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
69
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INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2
†‡
(see Figure 23)
NO.
PARAMETER
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN
MAX
1
tc(CKO2)
Cycle time, CLKOUT2
C2 − 0.8
C2 + 0.8
ns
2
tw(CKO2H)
Pulse duration, CLKOUT2 high
(C2/2) − 0.8
(C2/2) + 0.8
ns
3
tw(CKO2L)
Pulse duration, CLKOUT2 low
(C2/2) − 0.8
(C2/2) + 0.8
ns
4
tt(CKO2)
Transition time, CLKOUT2
2
ns
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
CLKOUT2
1
2
3
4
4
Figure 23. CLKOUT2 Timings
switching characteristics over recommended operating conditions for CLKOUT3
†§
(see Figure 24)
NO.
PARAMETER
GDPA-167
ZDPA−167
−200
−250
UNIT
MIN
MAX
1
tc(CKO3)
Cycle time, CLKOUT3
C3 − 0.9
C3 + 0.9
ns
2
tw(CKO3H)
Pulse duration, CLKOUT3 high
(C3/2) − 0.9
(C3/2) + 0.9
ns
3
tw(CKO3L)
Pulse duration, CLKOUT3 low
(C3/2) − 0.9
(C3/2) + 0.9
ns
4
tt(CKO3)
Transition time, CLKOUT3
3
ns
5
td(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid
1.5
7.5
ns
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register. For more details, see
PLL and PLL controller.
CLKIN
CLKOUT3
NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.
3
1
2
4
4
5
5
Figure 24. CLKOUT3 Timings