Synchronous dram timing (continued) – Motorola TMS320C6711D User Manual
Page 78
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TMS320C6711D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
78
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77251−1443
SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA12
EA[21:13]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
† ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 32. SDRAM Write Command
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