Siemens SPC3 - Manual (Page 52)

PROFIBUS Interface Center SPC3
Page 50 V1.3 SPC3 Hardware Description
2003/04 Copyright (C) Siemens AG 2003. All rights reserved.
Asynchronous Intel-Mode, Processor-Read-Timing
XRD
VALID
Data Out
AB(10..0)
DB(7..0)
XCS
XWR = log.'1'
23
28
22
25
21
24
XREADY
(normal)
XREADY
(early)
27
30
20
29
26
34
35
Asynchronous Intel-Mode, Processor-Write-Timing
XWR
VALID AB(10..0)
DB(7..0)
XRD = log.'1'
23
22
32
33
31
Data In
XCS
XREADY
(normal)
27
30
28
20
26
29
34
XREADY
(early)
36
37
8.5.4 Timing in the Synchronous Motorola Mode (E_Clock-Mode, for example, 68HC11) :
For a CPU clockline through the SPC3, the output clock pulse (CLKOUT2/4) must be 4 times larger than the
E_CLOCK. That is, a clock pulse signal must be present at the CLK input that is at least 10 times larger
than the desired system clock pulse (E_CLOCK). The Divider-Pin must be placed on <log. 0> (divider 4).
This results in an E_CLOCK of 3MHz.