Tablea.2 pci connector j1 (front), Pci connector j1 (front) – LSI U40HVD User Manual

Page 59

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Operational Environment

A-5

Table A.2

PCI Connector J1 (Front)

Signal Name

Pin

Signal Name

Pin

Signal Name

Pin

12 V

1

GND

22

+3.3 V

43

TCK

2

AD27

23

C_BE1/

44

GND

3

AD25

24

AD14

45

TDO

4

+3.3 V

25

GND

46

+5 V

5

C_BE3/

26

AD12

47

+5 V

6

AD23

27

AD10

48

INTB/

7

GND

28

GND

49

INTD/

8

AD21

29

KEYWAY

50

GND (PRSNT1/)

9

AD19

30

KEYWAY

51

RESERVED

10

+3.3 V

31

AD08

52

GND (PRSNT2/)

11

AD17

32

AD07

53

KEYWAY

12

C_BE2/

33

+3.3 V

54

KEYWAY

13

GND

34

AD05

55

RESERVED

14

IRDY/

35

AD03

56

GND

15

+3.3 V

36

GND

57

CLK

16

DEVSEL/

37

AD01

58

GND

17

GND

38

3 V/5 V

59

REQ/

18

LOCK/

39

ACK64/

60

3 V/5 V

19

PERR/

40

+5 V

61

AD31

20

+3.3 V

41

+5 V

62

AD29

21

SERR/

42

Note: Shaded signals are not connected.

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