Package outline, Packing information, Pbls4004d – NXP Semiconductors PBLS4004D User Manual

Page 11: Package outline 9. packing information, Nxp semiconductors

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PBLS4004D_3

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 03 — 6 January 2009

11 of 15

NXP Semiconductors

PBLS4004D

40 V PNP BISS loadswitch

8.

Package outline

9.

Packing information

[1]

For further information and the availability of packing methods, see

Section 13

.

[2]

T1: normal taping

[3]

T2: reverse taping

Fig 17. Package outline SOT457 (SC-74)

04-11-08

Dimensions in mm

3.0
2.5

1.7
1.3

3.1
2.7

pin 1 index

1.9

0.26
0.10

0.40
0.25

0.95

1.1
0.9

0.6
0.2

1

3

2

4

5

6

Table 8.

Packing methods

The indicated -xxx are the last three digits of the 12NC ordering code.

[1]

Type number

Package

Description

Packing quantity

3000

10000

PBLS4004D

SOT457

4 mm pitch, 8 mm tape and reel; T1

[2]

-115

-135

4 mm pitch, 8 mm tape and reel; T2

[3]

-125

-165

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