Texas Instruments DM648 DSP - Manual (Page 10)

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L1 S1 M1 D1
Data path A
Register file A Register file B
D2
Data path B
S2 M2 L2
L1 data memory controller
Cache control
Memory protection
Interrupt
and exception
controller
Power control
Instruction decode
16/32−bit instruction dispatch
Instruction fetch
SPLOOP buffer
C64x+ CPU
IDMA
Bandwidth management
Cache control
L1 program memory controller Advanced
event
triggering
(AET)
L2 memory
controller
Bandwidth
management
Memory
protection
registers
Configuration
L1P
cache/SRAM
L1D
cache/SRAM
PLL2
DDR2 memory
EMIFA
Other
peripherals
EDMA
Boot
configuration
Switched central resource
PLL2
L2 memory
controller
controller
memory
External
controller
DMA
Master
DMA
Slave
Cache
control
Bandwidth management
Memory protection
1.4 Industry Standard(s) Compliance Statement
Introduction
Figure 1. DDR2 Memory Controller Block Diagram
The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with the
exception of the On Die Termination (ODT) feature. The DSP does not include any on-die terminating
resistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled by
tying the ODT input pin of the DDR2 SDRAM memory to ground.
DSP DDR2 Memory Controller 10 SPRUEK5A – October 2007
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