Texas Instruments DM648 DSP - Manual (Page 36)

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4 DDR2 Memory Controller Registers
DDR2 Memory Controller Registers
Table 17 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data
manual for the memory address of these registers.
Table 17. DDR2 Memory Controller Registers
Offset Acronym Register Description Section
00h MIDR Module ID and Revision Register Section 4.1
04h DMCSTAT DDR2 Memory Controller Status Register Section 4.2
08h SDCFG SDRAM Configuration Register Section 4.3
0Ch SDRFC SDRAM Refresh Control Register Section 4.4
10h SDTIM1 SDRAM Timing 1 Register Section 4.5
14h SDTIM2 SDRAM Timing 2 Register Section 4.6
20h BPRIO Burst Priority Register Section 4.7
E4h DMCCTL DDR2 Memory Controller Control Register Section 4.8
36 DSP DDR2 Memory Controller SPRUEK5A – October 2007
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