Texas Instruments DM648 DSP - Manual (Page 12)

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DDR_D[31:0]
DDR2
memory
controller
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_DQS[3:0]
DDR_A[13:0]
DDR_VREF
DDR_DQGATE[3:0]
DDR_DQS[3:0]
DDR_ODT[1:0]
Peripheral Architecture
Figure 2. DDR2 Memory Controller Signals
Table 1. DDR2 Memory Controller Signal Descriptions
Pin Description
DDR_D[31:0] Bidirectional data bus. Input for data reads and output for data writes.
DDR_A[13:0] External address output.
DDR_CS Active-low chip enable for memory space CE0. DDR_CS is used to enable the DDR2 SDRAM memory
device during external memory accesses. DDR_CS pin stays low throughout the operation of the DDR2
memory controller; it never goes high. Note that this behavior does not affect the ability of the DDR2 memory
controller to access DDR2 SDRAM memory devices.
DDR_DQM[3:0] Active-low output data mask.
DDR_CLK/ Differential clock outputs.
DDR_CLK
DDR_CKE Clock enable (used for self-refresh mode).
DDR_CAS Active-low column address strobe.
DDR_RAS Active-low row address strobe.
DDR_WE Active-low write enable.
DDR_DQS[3:0]/ Differential data strobe bidirectional signals.
DDR_DQS[3:0]
DDR_ODT[1:0] On-die termination signals to external DDR2 SDRAM. These pins are reserved for future use and should not
be connected to the DDR2 SDRAM. Note: there are no on-die termination resistors implemented on the die
of this device.
DDR_BA[2:0] Bank-address control outputs.
DDR_DQGATE[3:0] Data strobe gate pins. These pins are used as a timing reference during memory reads. The
DDR_DQGATE0 and DDR_DQGATE2 pins should be routed out and connected to the DDR_DQGATE1 and
DDR_DQGATE3 pins, respectively. For more routing requirements on these pins, see the device-specific
data manual.
DDR_VREF DDR2 Memory Controller reference voltage. This voltage must be supplied externally. See the
device-specific data manual for more details.
DSP DDR2 Memory Controller 12 SPRUEK5A – October 2007
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