Texas Instruments DM648 DSP - Manual (Page 44)

www.ti.com
4.7 Burst Priority Register (BPRIO)
DDR2 Memory Controller Registers
The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory
controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of
the oldest command in the command FIFO after a set number of transfers have been made. The
PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller
raises the priority of the oldest command. The BPRIO is shown in
Figure 26 and described in Table 24 .
See Section 2.7.2 for more details on command starvation.
Figure 26. Burst Priority Register (BPRIO)
31 16
Reserved
R-0
15 8 7 0
Reserved PRIO_RAISE
R-0 R/W-0xFF
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Burst Priority Register (BPRIO) Field Descriptions
Bit Field Value Description
31-8 Reserved Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0 PRIO_RAISE Number of memory transfers after which the DDR2 memory controller will elevate the priority of the
oldest command in the command FIFO. Setting this field to FFh disables this feature, thereby
allowing old commands to stay in the FIFO indefinitely.
0 1 memory transfer
1 2 memory transfers
2 3 memory transfers
3-FEh 4-FFh memory transfers
FFh Feature disabled, commands can stay in command FIFO indefinitely
44 DSP DDR2 Memory Controller SPRUEK5A – October 2007
Submit Documentation Feedback