Texas Instruments TMS320C2XX - Manual (Page 21)

Figures
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11–2 ’C209 Interrupt Flag Register (IFR) — Data-Memory Address 0006h 11-12 . . . . . . . . . . . . . . .
11–3 ’C209 Interrupt Mask Register (IMR) — Data-Memory Address 0004h 11-13 . . . . . . . . . . . . .
11–4 ’C209 Timer Control Register (TCR) — I/O Address FFFCh 11-15 . . . . . . . . . . . . . . . . . . . . . .
11–5 ’C209 Wait-State Generator Control Register (WSGR) — I/O Address FFFFh 11-17 . . . . . . .
C–1 Procedure for Generating Executable Files C-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D–1 TMS320 ROM Code Submittal Flow Chart D-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–1 14-Pin Header Signals and Header Dimensions E-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–2 Emulator Cable Pod Interface E-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–3 Emulator Cable Pod Timings E-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–4 Emulator Connections Without Signal Buffering E-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–5 Emulator Connections With Signal Buffering E-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–6 Target-System-Generated Test Clock E-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–7 Multiprocessor Connections E-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–8 Pod/Connector Dimensions E-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–9 14-Pin Connector Dimensions E-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–10 Connecting a Secondary JTAG Scan Path to a Scan Path Linker E-17 . . . . . . . . . . . . . . . . . . .
E–11 EMU0/1 Configuration to Meet Timing Requirements of Less Than 25 ns E-21 . . . . . . . . . . . .
E–12 Suggested Timings for the EMU0 and EMU1 Signals E-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–13 EMU0/1 Configuration With Additional AND Gate to Meet
Timing Requirements of Greater Than 25 ns
E-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–14 EMU0/1 Configuration Without Global Stop E-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E–15 TBC Emulation Connections for n JTAG Scan Paths E-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .