Texas Instruments TMS320C2XX - Manual (Page 453)

Using the Instruction Set Comparison Table
B-4
Based on the device, this is how the indirect addressing operand {ind} is
interpreted:
{ind} ’C1x: { * | *+ | *– }
’C2x: { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– }
’C2xx: { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– }
’C5x: { * | *+ | *– | *0+| *0– | *BR0+ | *BR0– }
where the possible options are separated by vertical bars (|). For example:
ADD { ind }
is interpreted as:
’C1x devices ADD { * | *+ | *– }
’C2x devices ADD { * | *+ | *– | *0+ | *0– | *BR0+ | *BR0– }
’C2xx devices ADD { * | *+ | *– | *0+ | *0– | *BR0+ | *BR0– }
’C5x devices ADD { * | *+ | *– | *0+ | *0– | *BR0+ | *BR0– }
Based on the device, these are the sets of values for shift, shift
1
, and shift
2
:
shift ’C1x: 0–15 (shift of 0–15 bits)
’C2x: 0–15 (shift of 0–15 bits)
’C2xx: 0–16 (shift of 0–16 bits)
’C5x: 0–16 (shift of 0–16 bits)
shift
1
’C1x: n/a
’C2x: 0–15 (shift of 0–15 bits)
’C2xx: 0–16 (shift of 0–16 bits)
’C5x: 0–16 (shift of 0–16 bits)
shift
2
’C1x: n/a
’C2x: n/a
’C2xx: 0–15 (shift of 0–15 bits)
’C5x: 0–15 (shift of 0–15 bits)
In some cases, the sets are smaller; in these cases, the valid sets are given
in the
Description column of the table.