Texas Instruments TMS320C2XX - Manual (Page 544)

F-7 Glossary
decode phase: The phase of the pipeline in which the instruction is de-
coded. See also pipeline; instruction-fetch phase; operand-fetch phase;
instruction-execute phase.
delta interrupt: An asynchronous serial port interrupt (TXRXINT) that is
generated if a change takes place on one of these general-purpose I/O
pins: IO0, IO1, IO2, or IO3.
digital loopback mode: A synchronous serial port test mode in which the
receive pins are connected internally to the transmit pins on the same de-
vice. This mode, enabled or disabled by the DLB bit, allows you to test
whether the port is operating correctly.
DIM: Delta interrupt mask bit. Bit 9 of the asynchronous serial port control
register (ASPCR); enables or disables delta interrupts.
DIO0–DIO3 bits: Bits 4–7 of the IOSR. If the asynchronous serial port is en-
abled (the URST bit of the ASPCR is 1), these bits are used to track a
change from a previous known or unknown signal value at the corre-
sponding I/O pin (IO0–IO3). For example, DIO0 indicates a change on
the IO0 pin. See also
CIO0–CIO3 bits; IO0–IO3 bits.
direct addressing: One of the methods used by an instruction to address
data-memory. In direct addressing, the data-page pointer (DP) holds the
nine MSBs of the address (the current data page), and the instruction
word provides the seven LSBs of the address (the offset). See also
indi-
rect addressing.
DIV2/DIV1: Two pins used together to determine the clock mode of the ’C2xx
clock generator (
ч
2,
Ч
1,
Ч
2, or
×
4). (The ’C209 uses the CLKMOD pin
and has only two clock modes,
÷
2 and
×
2.)
divide-down value: The value in the timer divide-down register (TDDR).
This value is the prescale count for the on-chip timer. The larger the di-
vide-down value, the slower the timer interrupt rate.
DLB bit: Bit 0 of the synchronous serial port control register (SSPCR); en-
ables or disables digital loopback mode for the on-chip synchronous seri-
al port. See also
digital loopback mode.
DP: See data page pointer (DP).
DR bit: Data ready indicator for the receiver. Bit 8 of the I/O status register
(IOSR); indicates whether a new 8-bit character has been received in the
ADTR of the asynchronous serial port.
DR pin: Serial data receive pin. A synchronous serial port pin that receives
serial data. As each bit is received at DR, the bit is transferred serially into
the receive shift register (RSR).
Glossary