Texas Instruments TMS320C2XX User Manual

Page 555

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F-18

program control logic:

Logic circuitry that decodes instructions, manages

the pipeline, stores status of operations, and decodes conditional opera-
tions.

program counter (PC):

A register that indicates the location of the next

instruction to be executed.

program read bus (PRDB):

A 16-bit internal bus that carries instruction

code and immediate operands, as well as table information, from pro-
gram memory to the CPU.

PS:

Program select pin. The ’C2xx asserts PS to indicate an access to exter-

nal program memory.

PSC:

Timer prescaler counter. Bits 9–6 of the timer control register (TCR);

specifies the prescale count for the on-chip timer.

PSLWS:

Lower program-space wait-state bits. A value in the wait-state gen-

erator control register (WSGR) that determines the number of wait states
applied to reads from and writes to off-chip lower program space (ad-
dresses 0000h–7FFFh). PSLWS is not available on the ’C209; instead,
see

PSWS. On other ’C2xx devices, PSLWS is bits 2–0 of the WSGR.