Document Outline

• Introduction TO QPHY-DDR3
  • Required equipment
• Signals measured
  • CK, CK# Input
  • DQ Input/Output
  • DQS, DQS# Input/Output
  • CS# Input
• DDR3 MEASUREMENT PREPARation
  • Deskewing the Probes
  • Differential Probe Deskew Procedure using TF-DSQ on non-Zi oscilloscopes
  • Differential Probe Deskew Procedure on Zi oscilloscopes using PCF200
    • PCF200 Fixture Overview
    • Probe Connection to PCF200
    • Probe Calibration Procedure
• Basic Functionality
  • READ Burst Operation
  • WRITE Burst Operation
• Using Qualiphy DDR3
• QualiPHY Compliance Test Platform
  • Oscilloscope Option Key Installation
  • Typical (Recommended) Configuration
  • Remote (Network) Configuration
  • Oscilloscope Selection
  • Accessing the QPHY-DDR3 Software using QualiPHY
  • Customizing QualiPHY
  • QPHY-DDR3 Operation
• QPHY-DDR3 Test Configurations
  • 1) Clock tests DDR3-1333 (1 Probe)
  • 2) CKdiff-DQse-DQSdiff 1333 Write Burst (3 Probes)
  • 3) CKdiff-DQse-DQSdiff 1333 Read Burst (3 Probes)
  • 4) Eye Diagram (3 Probes Debug)
  • 5) Eye Diagram with CS Enabled (4 Probes Debug)
  • 6) CKDiff-DQse-DQS-ADD/CTRLse (4 Probes Debug)
  • 7) CKdiff-DQse-DQSp-DQsn (4 probes test, each DQS signal probed single ended)
  • 8) CKp-CKn-DQse-DQSdiff (4 probe test, each CK signal is probed single ended)
  • 9) Vref tests
  • D1) Demo of All Tests
• QPHY-DDR3 Variables
  • General Variables
    • DUT Speed Grade in MT/s
    • DQ Signal Name
    • DQS Signal Name
    • Clock Signal Name
    • DUT Power Supply VDDQ
  • 4th Probe Names
    • Chip Select Signal Name
  • Script Settings
    • Save Acquired Waveforms
    • Silent mode control
    • Stop On Test to review results
    • Use Chip Select (require one more probe)
    • Waveform Path
  • Latency Setting
    • Overall Read Latency
    • Overall Write Latency
  • Demo Settings
    • Use Stored Waveforms
    • Recalled Waveform File Index (5 digits)
    • Define format used to set trace names
    • Use Stored Trace for Speed Grade
  • Advanced Settings
    • Clock Period per Screen Division
    • Number of cycles for Clock test
    • Max. Number Of Samples Per Clock Period
  • Configuration Specific Variables
    • XX Channel Gain
    • XX Channel Index
    • XX Channel Invert
    • XX Channel Offset
  • Speed Bin Paramters
    • CAS Latency
    • CAS Write Latency
    • Speed Bin
• QPHY-DDR3 Limit Sets
  • DDR3-800
  • DDR3-1066
  • DDR3-1333
  • DDR3-1600
• QPHY-DDR3 Tests
  • Clock Tests
    • tCK(avg), Average Clock Period
    • tCK(abs), Absolute Clock Period
    • tCH(avg), Average High Pulse Width
    • tCL(avg), Average Low Pulse Width
    • tCH(abs), Absolute High Pulse Width
    • tCL(abs), Absolute Low Pulse Width
    • tJIT(duty), Half Period Jitter
    • tJIT(per), Clock Period Jitter
    • tJIT(cc), Cycle to Cycle Period Jitter
    • tERR(n per), Cumulative Error
  • Eye Diagram
    • Write Burst (Inputs)
    • Read Burst (Outputs)
  • Electrical Tests
    • Write Bursts (Inputs)
      • Slew (Input Slewrate)
        • SlewR and SlewF
      • Logic Levels
        • VIH(ac), maximum AC input logic high
        • VIH(dc), minimum DC input logic high
        • VIL(ac), maximum AC input logic low
        • VIL(dc), minimum DC input logic low
    • Read Bursts (Outputs)
      • SRQ (Output Slew Rate)
        • SRQr and SRQf
  • Timing Tests
    • Read Bursts
      • tDQSQ, DQS-DQ Skew for DQS and Associated DQ Signals
      • tQH, DQ/DQS Output Hold Time From DQS
      • tDQSCK, DQS Output Access Time from CK/CK #
    • Write Bursts
      • tDQSS, DQS latching rising transitions to associated CK edge
      • tDQSH, DQS Input High Pulse Width
      • tDQSL, DQS Input Low Pulse Width
    • tDSS, DQS Falling Edge to CK Setup Time
    • tDSH, DQS Falling Edge Hold Time from CK
    • tDS(base), DQ and DM Input Setup Time
    • tDH(base), DQ and DM Input Hold Time
  • Four Probe tests measurements using ADDR/CTL
    • tIS /tIH (base) - Address and Control Input Setup Time (Hold Time)
    • tIPW, Control and Address Input pulse width for each input
    • VIX(ac), AC Differential Input Cross Point Voltage