Figure 1. control port timing - i·c format, Figure 1.control port timing - i²c format – Cirrus Logic CS3318 User Manual
Page 10
10
DS693F1
CS3318
CONTROL PORT SWITCHING CHARACTERISTICS - I²C FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
7.
Data must be held for sufficient time to bridge the transition time, t
fc
, of SCL.
Parameter Symbol
Min
Max
Unit
SCL Clock Frequency
f
scl
-
100
kHz
RESET Rising Edge to Start
t
irs
100
-
ns
Bus Free Time Between Transmissions
t
buf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
t
hdst
4.0
-
µs
Clock Low time
t
low
4.7
-
µs
Clock High Time
t
high
4.0
-
µs
Setup Time for Repeated Start Condition
t
sust
4.7
-
µs
SDA Hold Time from SCL Falling
t
hdd
0
-
µs
SDA Setup time to SCL Rising
t
sud
250
-
ns
Rise Time of SCL and SDA
t
rc
, t
rd
-
1
µs
Fall Time SCL and SDA
t
fc
, t
fd
-
300
ns
Setup Time for Stop Condition
t
susp
4.7
-
µs
Acknowledge Delay from SCL Falling
t
ack
300
1000
ns
t
buf
t
hdst
t
lo w
t
hdd
t
high
t
sud
Stop
Start
SDA
SCL
t
irs
RESET
t
hdst
t
rc
t
fc
t sust
t susp
S ta rt
Stop
R e p e a te d
t
rd
t
fd
t
ack
Figure 1. Control Port Timing - I²C Format