Figure 2. control port timing - spi format, Figure 2.control port timing - spi format – Cirrus Logic CS3318 User Manual
Page 11
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DS693F1
11
CS3318
CONTROL PORT SWITCHING CHARACTERISTICS - SPI™ FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VD, C
L
= 20 pF)
8.
Data must be held for sufficient time to bridge the transition time of CCLK.
9.
For f
sck
<1 MHz.
Parameter
Symbol Min
Max
Unit
CCLK Clock Frequency
f
sck
0
6.0
MHz
RESET Rising Edge to CS Falling
t
srs
100
-
ns
CS High Time Between Transmissions
t
csh
1.0
-
μs
CS Falling to CCLK Edge
t
css
20
-
ns
CCLK Low Time
t
scl
66
-
ns
CCLK High Time
t
sch
66
-
ns
CDIN to CCLK Rising Setup Time
t
dsu
40
-
ns
CCLK Rising to DATA Hold Time
t
dh
15
-
ns
Rise Time of CCLK and CDIN
t
r2
-
100
ns
Fall Time of CCLK and CDIN
t
f2
-
100
ns
t
r2
t
f2
t
dsu
t dh
t sch
t scl
CS
MOSI
t css
t
csh
RESET
t srs
CCLK
Figure 2. Control Port Timing - SPI Format
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