Cirrus Logic CS4202 - Manual (Page 31)

CS4202
DS549PP2 31
4.13 Extended Audio Status/Control Register (Index 2Ah)
SPCV S/PDIF Configuration Valid. This read-only bit indicates the status of the S/PDIF transmitter
subsystem, enabling the driver to determine if the currently programmed S/PDIF configura-
tion is supported. SPCV is always valid, independent of the S/PDIF enable bit status.
SPSA[1:0] S/PDIF Slot Assignment. These bits control the mapping of output slots to the S/PDIF trans-
mitter. To satisfy AC ‘97 2.2 AMAP requirements, the default for these bits will depend on the
Codec ID as shown in Table 9 on page 30. See Table 8 on page 30 for all available Slot Map
settings.
SPDIF Enable Sony/Philips Digital Interface. This bit enables S/PDIF data transmission on the
SPDIF_OUT pin. The SPDIF bit routes the left and right channel data from the AC ’97 con-
troller or from the ADC output to the S/PDIF transmitter block. The actual data routed to the
S/PDIF block are controlled through the configuration of the SPSA[1:0] bits and the ASPM bit
in the AC Mode Control Register (Index 5Eh).
VRA Enable Variable Rate Audio. When ‘set’, the VRA bit allows access to the PCM Front DAC
Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h). This bit must
be ‘set’ in order to use variable PCM playback or capture rates. The VRA bit also serves as
a powerdown for the DAC and ADC SRC blocks. Clearing VRA will reset the PCM Front DAC
Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) to their default
values. The SRC data path is flushed and the Slot Request bits for the currently active DAC
slots will be fixed at ‘0’.
Default 0410h
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 SPCV 0 0 0 0 SPSA1 SPSA0 0 SPDIF 0 VRA