Cirrus Logic CS4202 - Manual (Page 64)

CS4202
64 DS549PP2
14. REFERENCE DESIGN
R18 6.8K
C23
1uF Y5V
R14
6 .8K
C31 22pF NP
O
C22
1uF Y5V
C32 22pF NP
O
J1
1 2
R11
6 .8K
R4
220K
J4
4 3 5 2 1
C25 2.2uF Y5V
C3 10uF ELEC
+
R9
47
Y1
24.576 MHz
R5
100K
J2
1 2 3 4
C10 0.1uF X7R
C6 10uF ELEC
+
C30
1uF Y5V
G ND_TIE
0.
050 i
n ch
R3
100K
C29 0.1uF X7R
J7
1 2
R20 1.5K
J6
1 2 3 4 5 6
R10 10K
R12
6 .8K
J3
4 3 5 2 1
R8
47
R17
6 .8K
C2 2700pF X7R C9
1uF Y5V
C19
220uF ELEC
+
U2
CS4202
LI
N E _OU
T _R
36
MO
NO
_ O UT
37
AVdd2 38
HP
_ O UT_
L
39
GPI
O 1/
SD
OU
T
44
HP
_ O UT_
R
41
AV ss2
42
GPI
O 0/
LR
C L K
43
HP
_ O UT_
C
40
GPI
O 4/ SD
O2
34
GPIO 3 33
GPI
O
2
32
HP
CFG
31
DV dd1
1
XTL_I N 2
XTL_OU T 3
DV
ss1
4
SD
AT
A_OU
T
5
BI
T _ C L K
6
DV
ss2
7
SD
AT
A_I
N
8
SYN
C
10
DV dd2
9
R
ESET
#
11
PC
_BEEP
12
PH
ON
E
13
AU
X_L
14
AU
X_R
15
VI
D E O_L
16
VI
D E O_R
17
CD_
L
18
CD_
C
19
CD_
R
20
MIC1
21
MIC2
22
LI
N E _I N _ L
23
LI
N E _I N _ R
24
AVdd1
25
AV ss1 26
RE
FFL
T
27
Vref
out
28
AF
LT
1
29
AF
LT
2
30
SPD
IF _OU
T
48
EAPD
/S
C L K
47
ID1
#
46
ID0
#
45
LI
N E _OU
T _L
35
C8
1uF Y5V
R2 4.7K
R1
47K
C14
1uF Y5V
R7
100K
C11 0.1uF X7R
C26 0.1uF X7R
C20
220uF ELEC
+
C15
1uF Y5V
U1
MC78M05ACDT
OU
T
3
GND
2
IN
1
J8
4 3 5 2 1
C28
1000pF
NP
O
C5 0.1uF X7R
R16
6 .8K
C27
1000pF
NP
O
J5 6 2 3 1 7
C16
1000pF NP
O
R13
10K
R15
10K
C18
1uF Y5V
R21
2 .2K
C17
1000pF NP
O
C13 0.1uF X7R
C21
1uF Y5V
C33 10uF ELEC
+
R6
220K
C4 0.1uF X7R
C24
NO
P
O P
R19 6.8K
C12 0.1uF X7R
C7
1uF Y5V
C1
0.1uF X7R
R ESET
#
SD
AT
AO
U T
SD
AT
AI
N 0
BI
T C LK
SYN
C
HP
S
E NS
E
AG
N D
AG
N D
AG
N D
DG
ND
AG
N D
AG
N D
DG
ND
DG
ND
AG
N
D
+3
.3
VD
DG
ND
DG
ND
+5
VD
AG
N D
AG
N D
DG
ND
AG
N
D
AG
N D
+5
VA
DG
ND
AG
N D
AG
N D
DG
ND
AG
N D
AG
N
D
+5
VA
+ 12V
DG
ND
+3
.3
VD
DG
ND
AG
N D
BEEP IN CD IN MIC IN LINE IN
H
EAD
PH
ON
E
JAC
K
S/PD
IF
OU
T
Ti
e at
one
poi
nt
onl
y
under
t he codec
(50 PPM)
PH
ON
E IN
LINE O
U
T
JAC
K
PC
I Audi
o
C
ont
ro
lle
r
o r IC
H
C
ont
ro
lle
r
AC LINK
For
2 channel
conf
igur
at
io
n
G
P
IO
3 (
p in
33)
is
ti
e d to
3.
3V.
2.
2uF capaci
tor
can
be r
epl
aced by t
w
o
1uF capaci
tor
s.
Figure 28.
CS42
02 Reference Design